ISEP | CISTER
29 de julho de 2013 l 11:00
O Centro de Investigação em Sistemas Confiáveis e de Tempo-Real (CISTER) traz Davit Mirzoyan (Delft University of Technology) ao ISEP para a próxima sessão da CISTER Distinguished Seminar Series. Agendada para 29 de julho, esta sessão aborda o tema “Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation”.
THROUGHPUT ANALYSIS AND VOLTAGE-FREQUENCY ISLAND PARTITIONING FOR STREAMING APPLICATIONS UNDER PROCESS VARIATION
Scaling technology into minimum feature size nodes has made it practically impossible to precisely control the manufacturing process, resulting in variation in performance characteristics of cores in a MPSoC. Conventionally, circuits are implemented with conservative design margins or guard-bands, often referred to as worst-case design, to guarantee the target frequency of each core in the manufactured chips. From an application´s perspective, the cores have deterministic frequencies, leading to a conventional application mapping, such that a certain timing requirement (e.g. throughput or latency) imposed on the system is satisfied. Guard-band reduction provides the benefits of reduced circuit area (i.e. a higher number of gross dies on a wafer), dynamic and leakage power. With reduced guard-bands, the target frequency of cores is not guaranteed any more, and the probability distribution of frequency needs to be considered when analyzing the system timing. Therefore, models and a methodology are required by system designers for evaluating the statistical timing of a system.
A framework is presented to estimate the probability distribution of application throughput (e.g. frames per second in video decoding) in a system with Voltage-Frequency Island (VFI) partitions in the presence of process variation. We use Synchronous Data-Flow (SDF) to model a system consisting of a real-time streaming application mapped to a MPSoC. A methodology to perform variation-aware partitioning of the cores of a MPSoC into VFIs for maximized timing yield is provided. The timing yield is a system-level metric showing the percentage of chips that satisfy a given throughput requirement imposed on the system. The use of the methodology is demonstrated for two purposes: 1) to make trade-offs between the number of VFI partitions (design cost) and timing yield; 2) to estimate the impact of reducing circuit design margins on the number of good dies (dies that satisfy the throughput requirement of a system) on a wafer.
DAVIT MIRZOYAN, DELFT UNIVERSITY OF TECHNOLOGY
Born in Yerevan, Armenia, in 1985. He acquired his B.Sc degree in Cybernetics from State Engineering University of Armenia (SEUA), located in Yerevan. He received his M.Sc degree in Information and Communication Technologies from Royal Institute of Technology (KTH), Sweden, Stockholm. His graduation project for the M.Sc program was carried out in Ikerlan, a research centre located in Arrasate, Spain. He is currently pursuing his PhD degree in Computer Engineering at Delft University of Technology, on the topic of variation-aware system-level design for streaming applications.