ISEP | CISTER
29 de abril de 2013 l 11:00

O Centro de Investigação em Sistemas Confiáveis e de Tempo-Real (CISTER) traz Orlando Moreira (ST-Ericsson, Eindhoven) ao ISEP para a próxima sessão da CISTER Distinguished Seminar Series. Agendada para 29 de abril, esta sessão aborda o tema “Making Data Flow Work for Real-time Wireless Communications”.

MAKING DATA FLOW WORK FOR REAL-TIME WIRELESS COMMUNICATIONS
This presentation focus on the challenges involved in the design of systems that provide timing guarantees to streaming applications, and, in particular, to wireless transceivers. We argue that the data flow model of computation is a convenient way of modelling and analysing modern streaming applications running on heterogeneous multiprocessors. We give an overview of timing-analysis techniques for data flow graphs. We then explain how hardware architectures and mapping decisions can be modelled in data flow and how, using the same analysis techniques, the timing behaviour of the mapped application can then be verified. These ingredients are used to build a model-based design-flow that maps a timing-constrained application onto a Multi-Processor System-on-Chip. State-of-the-art wireless transceiver applications (WLAN, LTE-A) are used to illustrate the data-flow-driven modeling, analysis and design flow. There is always an inherent difficulty in making abstract computation and analysis models fit real-life applications and platforms. We will point out some of these, and discuss solutions.

ORLANDO MOREIRA
Orlando Moreira is a Principal DSP Systems Engineer at ST-Ericsson, at the High Tech Campus site, in Eindhoven, The Netherlands. He graduated in Electronics Engineering from the University of Aveiro. In 2012, he received his Ph.D. degree in Electrical Engineering from the Eindhoven University of Technology. Before joining ST- Ericsson, he worked for Philips Research and NXP Semiconductors. In 2007-2008, he led a joint Nokia, NXP and ST-Ericsson team in developing a hard-real-time software architecture for radios. He has published papers on reconfigurable computing, real-time multiprocessor scheduling, resource management, data flow analysis and modelling. He was awarded patents in computer architecture and compilation methods.

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